Show HN: HW Synth with No Money

An ESP32-C3 reads MIDI, allocates voices and maps every knob to engine parameters. It writes those parameters over SPI to a Tang Nano 20K, where a single time-multiplexed datapath computes all 256 partials once per sample. Every musical decision is made in firmware; the FPGA only computes samples.

MIDI DIN 5-pin, opto

31250 bd

ESP32-C3 · CONTROL

MIDI parser · event bus voice allocator, 32 voices CC → parameter mapping patches: TOML on 4 MB flash bank / program change USB serial console 1 kHz tick · at most 1 ms latency

SPI 40 MHz parameter pages

TANG NANO 20K · SOUND

GW2AR-18C FPGA, 73.728 MHz 256-partial pipeline, 26 stages CSP: control program, 48 kHz passes 2 × SVF per partial, 12 / 24 dB log stereo attenuation · mix sat24 limiter · output LPF 768 clocks per sample

S/PDIF48 kHz optical I2S96 kHz DAC

Control plane in blue, audio in amber. The parameter image is double-buffered and swapped at sample boundaries, so a knob turn never lands mid-sample.

DMEM · 1024 WORDS · Q8.10 effective = base + dmem[pointer], saturating · pitch · duty · cutoff · 1/Q · gain L · gain R

OSCsaw pulse tri sineUQ0.24 phase SVF 1TPT / ZDFLP · BP · HP SVF 2cascade → 24 dBQ8.28 states L / R GAINattenuationset in dB MIX26-bit accsat24 limiter

× 256 partials per sample · parameters arrive from the control processor through data memory

256 partials per sample through a 26-stage pipeline.

Full-range modulationThe mod envelope can move cutoff by ±16 octaves and the cutoff control by ±8, so any destination can be driven end to end.

A small pipelined processor on the FPGA runs the envelopes, LFOs and modulation routings as one straight-line program, about 1,470 cycles per pass at 48 kHz, and writes the results into the partials' parameter memory.