From RTL and No-RTL to GDS in 3 Weeks

Pressing button on other people’s design only.

Downloaded vhdx image from Ishi-kai and converted to Docker image

Locally run example signoff flow in another Docker image from GitHub CI flow

Staring at inverter and kinda understood how it works, what are the layers mean.

Get idea about size of standard cells and total size available.

Understand the flow – what exactly xschem and klayout does, comparing with PCB, how to make sure schematics and layout matches.

Idea about the TDC which I never got time to do on FPGA.

Get to know ring oscillator and it’s one of the simple demos available

Understand why stdcell inverter is “huge”.

Understand what xschem can (gate-level simulation, inverter up/fall time) and can’t (for this, parasitic things, line delay) do.

Get to know PEX is not available but kinda not necessary here.

Learn what LVS does, quickly got that it’s really important!

Possibility about hierarchical schematics / sym / LVS – it’s certainly possible and recommended.

Based on Ishi-kai tutorials, get a inverter xschem simulation.

Then comes ring oscillator (RO) – simulated frequency ~150 MHz for 5 stages.

By adding another MOS, got a voltage-controlled oscillator simulation.

Got into tedious lab_pin, io_pin name conflict problems.

Wondering where to start klayout, if there’s a schematics-to-layout tool (no)

Connecting metal with an array of stdcell inverters.

Understand how MOS is a 4-port device, whether VSS/VDD is well connected, substrates, and how LVS handles this

Talked with team member about PDK histories.

I guess this is the day the tapeout decision was made.

Evaluate how much space is required, how many taps is available for TDC

Think about input delay of TDC, just think.

Understand what structure the I/O pads have (big ESD MOS)

TDC schematics passing xschem simulation, got ~2 ns per tap

Awful problem about LVS and pin names on GDS, cells in GDS, moving lines and vias breaking cells

LVS error when combining module into one, each module passes individually but the top module won’t

VSS/VDD metal wire width, from senior advice.

The LVS error was due to different cell names, solved by replacing all cells manually in child GDS module – not fundamental but works.

Placing a (photo)diode and get to know how it works, how the WN contact affects LVS – LVS really checks a lot of things!

Size of the diode, and why RC makes larger ones slow

Got to know friend’s librelane flow is close to signoff

DRC & GDS & GitHub CI passing with manually-placed designs (INV + RO + custom RO + VCO + TDC + Photodiode)

What to do with 1 left pin. Pressure-sensitive or microphone? Impossible.

Really thinking about the digital flow, targetting 20% chip space for a UART TX

Continue to analyze how much static characters can fit into the 20% chip space, various optimizations like all-capital characters and reuse counters. Even thought about a math formula to generate the characters – but no, same amount information is required anyways.

Really begin working on the librelane flow

Having RTL-GDS output, realized power problem are very different from FPGA!

Only one counter is used to drive from char selection to baud counting – this requires a very weird input frequency! Think about where the clock input comes due to the limited pins.

DRC/LVS clean UART GDS, outputting 24 big characters. See how the N-well are connected altogether.

Lots of optimizations and more examples with librelane flow

UART netlist gate-level simulation, see hazards in the combinatorial output, but seems OK

50 MHz clock is suspicious but 5 MHz works

Evaluate the 50 MHz-level clock compared with previous RO frequency

Compare how 130 nm/55 nm scales the frequency

Understand Power Distribution network needs special care in ASIC

DRC/LVS works but foundry IP62 DRC have error, then fixed this

Pull Requested minor fix to https://github.com/kadomoto/picture-to-gds

Pull Requested to https://github.com/luyanna/TR-1um libreline flow upstream, including GitHub CI