GPT-Synopsys Combines IC Design EDA with Agentic AI

AI integrations in EDA tools have mostly been internally developed models offered by EDA companies and fabs. In chip design workflows, agentic AI technologies currently connect general-purpose models to EDA tools. The next logical step will inevitably involve frontier AI models running the tools as expert engineers while iteratively optimizing chip designs.

Enter GPT-Synopsys, a specialized AI model optimized for Synopsys EDA tools to perform semiconductor design workflows using OpenAI’s frontier models. At its 2026 Investor Day in New York, Synopsys announced it is pairing its EDA tools and agentic AI capabilities with OpenAI’s advanced AI capabilities to move from AI-assisted design engineering toward domain-specific intelligence embedded directly within the IC design engineering workflow.

GPT-Synopsys uses OpenAI’s frontier models to operate directly in Synopsys’ EDA tools, reasoning about chip design and verification. It takes a leap of faith by combining frontier AI with deep EDA domain knowledge to take a crucial step toward truly AI-native chip design. GPT-Synopsys, for instance, could handle the rigorous precision required for physical synthesis and timing closure while leveraging GPT’s generative capabilities.

GPT-Synopsys will be trained and tuned specifically for chip design tasks, from describing the chip’s circuits in a code-like language to determining how to lay out billions of transistors on a small square of silicon. It will support EDA workflows, including power, performance and area (PPA) optimization, timing closure, and verification.

OpenAI will license Synopsys’ EDA tools to develop the specialized model. “We’re using our most advanced technology for chip design, helping engineers explore more designs and get to a working chip faster,” said Greg Brockman, president and co-founder of OpenAI.

While announcing the launch of GPT-Synopsys in collaboration with OpenAI, Sassine Ghazi, president and CEO of Synopsys, called for a dramatic acceleration of the chip design process without compromising PPA or first-time-right silicon. “Together with OpenAI, we’re bringing frontier intelligence to chip design to help more companies develop and accelerate advanced silicon, while maintaining the rigor and trust required for manufacturing success.”

With GPT-Synopsys, design engineers can delegate design objectives, such as PPA optimization, to agents that run the tools and review the verified outcomes. For instance, design engineers can specify objectives such as PPA optimization, timing closure, and verification closure. Next, agents will run tools, interpret results, make changes, and repeat the process for engineer review.

On OpenAI’s side, its model will learn how to ⁠use Synopsys EDA tools to help engineers work through the various tradeoffs and optimizations that happen during the chip design process. GPT-Synopsys—running on OpenAI-hosted infrastructure—will also be integrated with Synopsys.ai and the Synopsys Autopilot agentic AI platform.

Specialized models for chip design, such as GPT-Synopsys, could compress schedules that currently take months of a design engineer’s time. For instance, OpenAI’s model could learn to ⁠use Synopsys EDA tools to help engineers work through the tradeoffs and optimizations that happen during the design process. That, in turn, could shave off weeks, even months, from the IC design process.

However, Synopsys emphasizes that a company’s proprietary IC design data will remain protected through enterprise-grade security measures. Synopsys will not use proprietary IC design data to train the AI frontier model; moreover, the encrypted data can be managed through configurable retention, audit, and permission controls.

The design service jointly offered by Synopsys and OpenAI will bundle compute, the model, and EDA licenses while protecting customer-specific design data. It will protect customer, partner, and Synopsys IP through access controls, encryption, and runtime guardrails.

The tie-up between Synopsys and OpenAI establishes a shared revenue framework, an unusual arrangement signaling a high degree of financial commitment from both OpenAI and Synopsys to this collaboration. OpenAI will pay Synopsys a training subscription fee for learning to use Synopsys tools.

Next, when a company uses GPT-Synopsys, Synopsys and OpenAI will share revenue based on how well the ⁠model improves chip design. In other words, this two-pronged revenue model includes tool subscriptions related to frontier model training and covers tool subscriptions or consumption charges, plus revenue sharing from the use of those models.

The two companies will jointly benefit from sales of the specialized AI model, and as a result, their joint investment will go beyond the product launch. That shows how the two companies are willing to share both the risk and the reward.

Chip design cycles are long, which makes Synopsys’ OpenAI partnership a wild card. It’s more than a chatbot launch. The multi-year agreement to jointly develop GPT-Synopsys marks a new era in IC design, where EDA vendors such as Synopsys are now selling a new layer of AI-assisted design on top of the EDA tools IC designers already use.

However, it’s just the beginning. It remains to be seen how frontier models such as GPT-Synopsys learn to run EDA tools like expert engineers, interpret their outputs, and iteratively optimize designs using them.

Nevertheless, it’s an exciting step toward AI-native IC design engineering.

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RELATED TOPICS: AGENTIC AI, AI MODELS, CHIP DESIGN, CHIP VERIFICATION, DESIGN TOOLS (EDA), ICS, SEMICONDUCTORS

Majeed Ahmad, Editor in Chief of EDN and Planet Analog, has covered electronics design industry for longer than two decades. During this period, he has worked in various editorial positions, including assignments for EE Times Asia and Electronic Products. He holds a Masters’ degree in telecommunication engineering from Eindhoven University of Technology. Follow Majeed on LinkedIn

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